IntelliSuite White Paper

Process information: Ability to easily incorporate process tolerances and process corners. SPC information is often not available for Monte Carlo simulations.

High-fidelity models: Ability to include high-fidelity models which fully capture multiphysics effects. Users need to capture effects of packaging, fluidic damping, temperature gradients and other non-idealities such as electrostatic gradients or stiction that can greatly influence the device performance.

Limited libraries: Typical design libraries are limited in nature, and adding new components is a significant undertaking. While complex structures can be composed using basic shapes, schematic layout becomes an issue. Many MEMS schematic editors are little more than warmed-over IC design tools and are inefficient for MEMS design.

Ability to work with your favorite toolset: Lack of true standards among EDA vendors has led to the creation of multiple quasi-standards, each of which has significant disadvantages. MEMS tools must support many of these quasi-standards including SPICE and its variants (PSPICE, HSPICE, ELDO), Verilog (-A, -AMS, SystemVerilog), VHDLAMS (accounting for subtle but significant differences between tools) , and Matlab/Simulink.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Co-simulation with other system simulators: While system-level simulators such as SYNPLE or System Vision provide sophisticated functionality, there is a need for cosimulation along with other system simulators which may contain IP blocks or functionality not present in the tool of choice. The ability to mix system simulators such as SYNPLE with Simulink or Spectre will be extremely useful. 

Layout tools: Popular layout tools like Virtuoso or L-Edit were originally developed for the IC world. Other tools such as AutoCAD were developed for architectural and mechanical drawing and are a bear to use for mask layout. Beziers, splines, and smooth transitions (essential for minimizing stresses) are often absent or an afterthought in MEMS layout editors.

High quality layout automation: While schematic to mask synthesis exists in various tools, the resultant layouts are not production ready. Features such as smooth transitions, stress relief structures, release hole patterns, dimples and other secondary features need to be manually added to the layouts. This is often very time consuming.

Geometry manipulation and meshing: Design analysts spend a significant amount of time manipulating design geometries and meshing structures. Most MEMS design tools require manually partitioning 3D geometry into mesh-able regions. While many tools provide automated tetrahedral meshes, they are sub-optimal for MEMS design. In the words of a Sandia Labs design analyst, “The only people who use tets are those who don’t care about their answers”. Hexahedral meshes are ideally used for MEMS. The automatic generation of hex meshes has been the holy grail of the meshing community and is still a few years away.

 

Parametric meshing: Any parametric changes to the MEMS geometry such as changing a film thickness or electrode gap requires a complete re-meshing of the structure. Parametric meshing and mesh morphing technologies are relatively new and are just making their way into MEMS design tools.

Incorporation of process corners into physical design: As mentioned before, absence of reliable SPC data forces the designer to consider process corners based upon historical estimates of process tolerances. Users must manually configure their meshes for each of the process corners and run each process corner individually. This is highly time-consuming. 

Process flow modeling: Process engineers still spend a significant amount of time hand-drawing process flows in Powerpoint, Illustrator or some such tool. Any change in the process flow requires starting afresh in compiling the flow diagrams. While 3D process visualization and virtual prototyping was introduced by IntelliSense in 1995, full 3D visualization is time-consuming for large MEMS devices. There is a need to obtain 2D cross sections of custom process flows with minimal computing overhead. Better yet, automatic assembly of Powerpoint presentations would greatly simplify the process flow modeling.

 

Integrated cost and economics modeling: Cost and economics are often an afterthought during the design process. Any changes to the design, process, or package configurations requires re-running Excel spreadsheets. Trade-offs between various configurations become difficult to envision without years of expertise. At present, design and process engineers have little or no visibility into the cost equation. Empowering engineers to make economically sound decisions can go a long way in squeezing gross margins out of the product.

Deep Silicon Etch Simulations: Deep Reactive Ion Etching (DRIE) is here to become the main stay of MEMS process technology. First generation DRIE simulation tools such as RECIPE and RECIPE3D can be used to fine tune sidewall angle of structures locally. Manual mask corrections need to be applied to ensure uniform etching across the die. Next generation tools, similar to optical proximity correction tools for lithography, are needed to automatically correct the masks to ensure uniform local etching of devices.

Incorporating accurate process details into meshes: While tools like FABViewer™ and MEMulator™ can produce realistic device renderings, FEA meshing is often based upon idealized geometries rather than true geometries. Better meshing algorithms are needed to automatically create realistic meshes that are efficient to use in FEA simulations.

Enhanced ROMs: System model extraction techniques have improved over the years from simple linear macromodels to accurate non-linear reduced order models (ROMs) that can accurately capture stress stiffening, electrostatic spring softening, and fluid damping. With the advent of wafer-level packaging and demand for low-profile MEMS for mobile applications, more and more of the packaging functionality is being subsumed into the MEMS. Packaging effects like temperature/stress effects and shunt capacitance calculations need to be automatically included into the reduced order models.

Parametric ROMs: While the use of high fidelity ROMs in system simulation has gained adoption, ROMs suffer from the disadvantage of being tied to the original geometry. In a sense they are black box models. Users may prefer to have control over some of the device parameters, such as material thickness or electrode separations, for system level optimization scenarios. This necessitates the creation of parametric ROMs. Parametric ROMs can be derived using Latin Hyperspace (LHS) based design exploration followed by automatic fitting into a response surface for use in system simulators.

Optimization tools: While most CAD/EDA tools provide links to third-party optimization tools such as ModeFrontier, iSight or ModelCenter, the adoption of these tools into the MEMS design flow is non-existent. Impediments include poor integration, a steep learning curve, and the lack of optimization training in the MEMS industry. Many of these impediments can be solved by tightly integrating these tools into the design workflow and significantly simplifying the optimization setup.

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